Integrated circuits often include delay chains that are used to provide timing delays. For example, integrated circuits may include delay-locked loops having delay chains. These delay chains can be adjusted so that their delays are matched to a reference delay. Other delay chains are adjusted so that their delays are multiples or fractions of a reference delay.
Conventional delay chains are formed to provide equal rise and fall delays. Examples of conventional delay chains include chains of current-starved inverters, chains of shunt capacitor inverters, and delay interpolators. These delay chains provide adjustable delays that are controlled by digital control signals or analog control signals. As an example, a given chain of current-starved inverters may receive at its input a clock signal with a 25% duty cycle. The given chain should generate at its output a delayed version of the clock signal with a 25% duty cycle if the rise and fall delays are matched.
Modern integrated circuits may suffer from aging effects such as bias temperature instability (BTI). Such aging effects may cause the behavior of transistors to degrade over time (i.e., transistors may exhibit threshold voltage increases and a corresponding decrease in performance).
Integrated circuits such as programmable integrated circuits often include delay chains. Programmable integrated circuits have memory elements that are loaded with configuration data. The memory elements that are loaded with configuration data supply corresponding static control signals. The delay chains on a programmable integrated circuit may receive the static control signals for long periods of time (e.g., static control signals may have fixed polarities for at least six months). Transistors in the delay chains are subject to aging effect if the delay chains are stressed with static signals under extended periods of time, thereby causing the delay chains to exhibit different rising and falling delays. If these delay chains are used to delay clock signals, the delayed clock signals will undesirably suffer from duty cycle distortion.
As an example, a given chain of shunt capacitor inverters may receive at its input a clock signal with a 50% duty cycle. The given chain exhibits different rise and fall delays as a result of aging effects. The given chain will therefore generate at its output a distorted version of the clock signal, e.g., with a 55% duty cycle, if the rise and fall delays are unmatched.